cyclone3 : maximum DDR input rate with LVDS

Thanks for sharing your experiences.

I assume your reason for saying I only need the one clock channel (and not an additional inverted one) is that the innards of the FPGA can capture data on both the rising and falling edges (somehow). Otherwise, I don't understand, because the data is DDR, meaning a new bit is provided on each data-lane for both edges of the clock.

What is SDC?

Also, are you saying that once I experiment to achieve a good solid setup, we do not need to rebalance or actively fiddle the clock or data delays on each assembled product? Or we must make this process of sending in test patterns and trying different delays as part of our startup routine in the FPGA?

From my quick view, except for the dedicated serial inputs on the cyclone4, the cyclone4 parts are no faster than the cyclone3 parts. This is extremely strange to me, but that's what I believe I'm seeing. The other reason the cyclone4 parts seem useless to me is, they (the smaller units) only have 4 dedicated serial inputs, and with the HiSPi interface that has 4 data and 1 clock lane, I would need 5 of them to make a sensible design. Also, it seems off hand these dedicated serial inputs are configured to recover clocks from data, not have a dedicated clock lane to complement the data (like the HiSPi interface has).

I guess I could try some kind of simulation, but probably trying one with the real MT9J003 image sensor would be just about as easy (with its test patterns), and more definitive. Or not?