Honored Contributor
Honored ContributorHi,
I obtained a data sheet from the MT9J003. We have some experience with serial high-speed octal ADCs with LVDS outputs. So far I managed to interface these at 300 MHz with CycloneII C6 devices. I expect that the CycloneIII C6 devices should handle the 360 MHz from this sensor. The sensor has a provision to shift the clock channel in respect to the data channels and shift separate data channels, helping in aligning the data into the FPGA. Unfortunetaly there is no separate framing lane, so you have to sync on the fly or use the training patterns to align the words. You can do with the single clock channel provided, it is well centered in the middle of the data and you don't need a pll to shift the incoming clock to capture the data correctly. It may take a while to constrain the inputs (SDC) but it will work reliably in the end. The sensor has nice test-data patterns to help. Cyclone IV may be better and/or faster to constrain. I suggest you just start a small deserialiser project and simulate it .
