Cyclone V Transceiver Synchronised 32bit Word Alignment Problem

I still haven't managed to get this to work and I am waiting to here back from Altera through a service request on this.

I did try a similar method to this one (http://www.alteraforum.com/forum/showthread.php?t=21586&p=154036#post154036) identified on a Stratix IV using the following settings:-

• Word Aligner Pattern Length = 20 (x2 10b symbols)

• Word Aligner Pattern = AA97Ch (D10.2 & K28.5 negative disparity in LSbit serial order)

I could see the new word alignment working but I still couldn't get the byte (word) ordering to work looking for K28.5 (1BCh). I thought the word ordering might require an 18bit pattern (i.e. x2 data octets + x2 control symbol flags) but the megawizard insists that it requires a 9bit pattern.

To get around this issue I have written my own word ordering function, here is the simplified vhdl:-

architecture behaviour of RxBuffer is
    -- Word ordering (WO) signals
    signal WODetector       : std_logic;
    signal WODataDelta      : std_logic_vector(15 downto 0);
    signal WOData           : std_logic_vector(31 downto 0);
begin
    --  Re-Align detection register
    -- Note: when the dword is not synchronised this is asserted when the upper-word is synchronised and identifies the pattern
    --       detect (LSB) from the word aligner when the lower-word is not synchronised (prior to the pattern detector).
    process (SIMPLTP_RxClk) is
    begin
        if (rising_edge(SIMPLTP_RxClk)) then
            -- Check if the data word is not synchronised (one or more octets within the dword) = capture align detection
            if (SIMPLTP_RxData(58) = '0' or SIMPLTP_RxData(42) = '0' or SIMPLTP_RxData(26) = '0' or SIMPLTP_RxData(10) = '0') then
                WODetector <= -- Upper word synchronised and pattern detected
                              SIMPLTP_RxData(58) and SIMPLTP_RxData(44) and SIMPLTP_RxData(42) and
                              -- Lower word not synchronised
                              not SIMPLTP_RxData(26) and not SIMPLTP_RxData(10);
            else
                WODetector <= WODetector;
            end if;
        end if;
    end process;
    --  Data/control delta registers
    process (SIMPLTP_RxClk) is
    begin
        if (rising_edge(SIMPLTP_RxClk)) then
            WODataDelta <= SIMPLTP_RxData(55 downto 48) & SIMPLTP_RxData(39 downto 32);
        end if;
    end process;
    --  Word (re)alignment output register
    -- Note: either re-aligned or straight depending on the re-alignment detector
    process (SIMCL_Reset, SIMPLTP_RxClk) is
    begin
        if (SIMCL_Reset = '1') then
            WOData <= x"00000000";
        elsif (rising_edge(SIMPLTP_RxClk)) then
            -- Check if a re-alignment is detected and synchronisation established = use delta + current words
            if (WODetector = '1') then
                WOData <= SIMPLTP_RxData(23 downto 16) & SIMPLTP_RxData(7 downto 0) & WODataDelta;
            -- Re-Align not required = retain word order
            else
                WOData <= SIMPLTP_RxData(55 downto 48) & SIMPLTP_RxData(39 downto 32) &
                          SIMPLTP_RxData(23 downto 16) & SIMPLTP_RxData(7 downto 0);
            end if;
        end if;
    end process;
    --  Physical layer receive buffer data path output
    SIMPLRB_Data <= WOData;
end architecture;