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Altera_Forum
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12 years ago

Cyclone V SX Cascading PLL for LVDS

Hi, I'm currently working on a Cyclone V SX and i've got a little problem regarding LVDS clocking. I've got a 33 MHZ clock feeding my FPGA from the bottom bank 3A and I want to drive LVDS ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I am wondering if it is a bug with 13.0sp1 because I don't have this error with 13.0 on previous project.

I will test with 13.0 when I have time.