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Altera_Forum
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12 years ago

Cyclone V SX Cascading PLL for LVDS

Hi, I'm currently working on a Cyclone V SX and i've got a little problem regarding LVDS clocking. I've got a 33 MHZ clock feeding my FPGA from the bottom bank 3A and I want to drive LVDS ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

hi,

I met the similar error today. While I am using quartus II 13.0sp1 with Arria V. what quartus II version are you using?