Cyclone V Quartus II 14.0 partial reconfiguration

Hi,

Apologies for not responding to my own thread! It has taken a long time to get my head around this problem. Out of interest which particular variant of the Cyclone V SoC are you trying to enable partial reconfiguration on (it does make a difference!)

Following the Altera SoC Developers Conference, Frankfurt in October I have released a paper regarding some of the work I have done on this topic which may be found here:

https://www.altera.com/events/northamerica/altera-soc-developers-forum/technical-content.html#innovate-with-soc-fpgas----synchronized-networking-and-processing-on-an-soc-fpga

It is the "developing and implementing dynamic partial reconfiguration for pre-emptible context switching and continuous end-to-end dataflow applications" presentation and paper. Which may help to give you slightly more understanding of what I have achieved using the DE1-SoC.

Hope some of this helps.

Alex