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Honored Contributor
Honored ContributorCyclone V PLL desired output frequency
Hi! I have a problem using Altera PLL V 12.1 megafunction for Cyclone V. I choosed integer type of PLL and typed 20 MHz for Reference Clock Frequency. After that I choosed two output clock, ...
Altera_ForumHonored Contributor
Honored ContributorThe PLLs are not really designed to operate an output at such a low frequency. If it is a clock signal you need to provide on an output, you can generate it from a higher frequency using a counter, and if you need to use it inside the FPGA you can use a clock enable, also with a higher frequency clock.
