Cyclone V Fractional PLLs don't output expected clock frequency

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So I entered the physical parameters manually and it said it could achieve a frequency of 148.4999999MHz. I'm fine with that.

So I tried to synthesize the design and I am getting an absolutely bizarre synthesis error:

Error (13305): Verilog HDL error at altera_pll.v(2163): can't find port "refiqclk_1" File: c:/altera/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 2163

This isn't even one of my source files!! O.o

I have attached the file that the megawizard generated. I'm not sure what else to say...how can I compete with source files errors in Quartus' own installation directory..........?????

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This looks like an altera library problem. I looked at the same file in my 16.0 install, and I see in the altera_pll.v file:

            altera_cyclonev_pll# (
...
                )
                cyclonev_pll (
...
                // cyclonev_pll_refclk_select pins
                .adjpllin(adjpllin),    
                .cclk(cclk),
                .coreclkin(),
                .extswitch(extswitch),
                .iqtxrxclkin(),
                .plliqclkin(),
                .rxiqclkin(),
                .clkin({2'b0,refclk1, refclk}),
                .refiqclk_0(),
                .refiqclk_1(),
                .clk0bad(clkbad_wire),
                .clk1bad(clkbad_wire),
                .pllclksel(activeclk_wire),
                // cyclonev_pll_reconfig pins

so it expects refiqclk_0 and refiqclk_1 to be two separate one bit wide ports. But in the referenced altera_cyclonev_pll.v module file I see:

module altera_cyclonev_pll(
...
    clkin,        // 4
    refiqclk_0,    // 2
...
);
...
    input  clkin;
    input  refiqclk_0;
...

that refiqclk_0 is a single port that is two bits wide, and refiqclk_1 is a port that does not exist. So there is an inconsistency/error in the base altera library definition files. So it would appear that anybody that has tried to use a fractional PLL in a CycloneV would be getting this error, at least in 16.0 and thru 17.0.2.

This is a problem altera needs to fix. However, in the short term one could probably just comment out the reference .refiqclk_1(), on line 2163 of file altera_pll.v as a quick fix, as the ports are not connected and in this context do nothing useful.