Cyclone V ALTLVDS_TX: MSB inversion and timing constraints

Ok, I compiled the simplified design and run it on some test hardware and there is no such strange effect, a bit pattern of 1100 generates a signal with 50% duty cycle as expected. I had to use other pins and a lower frequency than on the real design though, so it may not be completely representative. No idea what's wrong there. At least I know that I must look out for this in future designs, as it could save some debugging.