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Altera_Forum
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9 years ago

Cyclone V ALTLVDS_RX output clock at half the expected rate

I am using Quartus Prime Standard for a Cyclone V design to instantiate an interface to an 8 channel 12-bit ADC in 2-wire mode. I'm using the ALTLVDS_RX megafunction and I have configured it for 16 c...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Well, log this one away as user error. It turns out, due to a totally unrelated issue, the input clock was at half the rate I expected...therefore the output clock was at half the rate I expected.