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Altera_Forum
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9 years ago

Cyclone V ALTLVDS_RX output clock at half the expected rate

I am using Quartus Prime Standard for a Cyclone V design to instantiate an interface to an 8 channel 12-bit ADC in 2-wire mode. I'm using the ALTLVDS_RX megafunction and I have configured it for 16 c...
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Altera_Forum
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9 years ago

Interesting. This is related to a post I just made regarding ALTLVDS_RX. What I can tell you is that if you use the MegaWizard GUI to instantiate an ALTLVDS_RX module, and you choose to use an external PLL, it will tell you that you need to apply;

1) (rx_inclock) a fast clock at the data rate = 360Mhz

2) (rx_enable) a slow (framing) clock = 60Mhz (with a specified duty cycle)