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Altera_Forum
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12 years ago

Cyclone PLL output clock pin assignment

Hi, I am using Cyclone IV E FPGA. There are four PLLs on the chip at four corners of the chip respectively. My first question, how many off-chip output clocks are there for each dedicated PLL? ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Hi Yaotin:

The PLLx_CLOCKOUTp and n outputs can be defined as differenetial or singled ended outputs.

So the PLLx_CLOCKOUT is dedicated PLL's output, which should only be sourced by that PLL which is drivin by a CLKx input pin associated with that PLL.

Not every PLL will always have dedicated PLLx CLOCKOUT's.

Every PLL will have 4 dedicated CLK-in's (Or 2 differential pairs)

So Care should be taken to make sure you are using the correct output pin so all the routing will be optimized.

Depending on the family you can break these rules, but at the cost of jitter performance, and max freqeuency.

In the past I have driven the dedicated clock out's from two various PLL clock outputs independently, but this could be family related as well. You may want to test this and verify it works.

Pete