New Contributor
Regular ContributorHello,
The term cmos33_cio_d2 is (in a_b_c form):
a. 3.3 LVCMOS
b. Column IO
c. 2mA drive strength.
The term d2 stands for drive strength of 2mA in this model. May I know how did you get driver output resistance?
Thank you.
New ContributorHi Amit,
You can approximate the output resistance as follows:
(1a) Is the process that I described correct? If not, what is the correct process to determine output resistance of the driver?
(1b) From the output resistance calculation as described above, the output resistance for cmos33_cio_d2 is coming more than 50 ohms. In such case, can we use source series termination? If yes, what value would you use because for 50 ohms characteristics impedance (Zo), Rs = Zo - Rdriver.
(2) So as per your reply, does it mean that the maximum drive strength of 3.3V LVCMOS is only 2mA? This is weird as this value is too small. We normally have lvcmos drive strength as 8mA or 12mA as typical values for driving 50 ohm transmission lines.
Thanks n Regards,
Binayak
Regular ContributorHello,
(1a) Is the process that I described correct? If not, what is the correct process to determine output resistance of the driver?
(1b) From the output resistance calculation as described above, the output resistance for cmos33_cio_d2 is coming more than 50 ohms. In such case, can we use source series termination? If yes, what value would you use because for 50 ohms characteristics impedance (Zo), Rs = Zo - Rdriver.
May I know how did you get this resource to determine the output resistance of the driver? You may use source series termination under certain conditions. You may refer more details on this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51006.pdf
(2) So as per your reply, does it mean that the maximum drive strength of 3.3V LVCMOS is only 2mA? This is weird as this value is too small. We normally have lvcmos drive strength as 8mA or 12mA as typical values for driving 50 ohm transmission lines.
The d2 in the acronym means 2mA drive strength for fast slew rate. You can view the naming method from Cyclone IV Models User Guide from this link: https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/ibis/ibs-ibis_index.html
New ContributorHi,
Please see my reply inline to your follow-up questions.
(1a) Is the process that I described correct? If not, what is the correct process to determine output resistance of the driver?
(1b) From the output resistance calculation as described above, the output resistance for cmos33_cio_d2 is coming more than 50 ohms. In such case, can we use source series termination? If yes, what value would you use because for 50 ohms characteristics impedance (Zo), Rs = Zo - Rdriver.
May I know how did you get this resource to determine the output resistance of the driver? You may use source series termination under certain conditions. You may refer more details on this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51006.pd...
[Binayak]: It's just based on simple voltage divider electrical circuit. Say a 3.3V driver outputs a 3.3V step edge. It will produce a step edge of half of 3.3V (1.65V), when you add an external series resistor equal to the output resistance of the driver inside the chip.
(2) So as per your reply, does it mean that the maximum drive strength of 3.3V LVCMOS is only 2mA? This is weird as this value is too small. We normally have lvcmos drive strength as 8mA or 12mA as typical values for driving 50 ohm transmission lines.
The d2 in the acronym means 2mA drive strength for fast slew rate. You can view the naming method from Cyclone IV Models User Guide from this link: https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout...
[Binayak]: I have seen the I/O tables. The 3.3V LVCMOS only has drive strength of 2mA. Really don't know how you can drive 50 ohms transmission lines such low drive strength.
Thanks n Regards,
Binayak
