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Altera_Forum
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12 years ago

Cyclone IV no JTAG access after PS configuration

Hi I use passive serial configuration for a EP4CE10F17C8 device (a DSP controls the nSTATUS, nCONFIG, DCLK and DATA0 ports of the FPGA) After configuration the FPGA releases CONF_DONE as it sho...
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Altera_Forum
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12 years ago

I am using 12.1 and 13.0 concurrently and experience the problem on either version.

There seem to be a magic number "set_output_delay -clock altera_reserved_tck -add_delay 20 [get_ports {altera_reserved_tdo}]". I do get a timing error of -14ns slack when it fails versus a good case it won't show up in TimeQuest report, so I really wonder if this number needs to be tweak for different devices we use.

Jeng