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Altera_Forum
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13 years ago

Cyclone IV no JTAG access after PS configuration

Hi I use passive serial configuration for a EP4CE10F17C8 device (a DSP controls the nSTATUS, nCONFIG, DCLK and DATA0 ports of the FPGA) After configuration the FPGA releases CONF_DONE as it sho...
Altera_Forum's avatar
Altera_Forum
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13 years ago

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I am getting similar issue on Arria V evaluation board as well but mainly by programming thru SignalTap. The only workaround I found so far is shuffle around the SignalTap buses, and re-compile. Next time around a good chance is it will work, but also a fairly high 25% chance more time to be wasted. My device is only about 1/3 full but it takes an hour to compile...

I wonder if the re-compile at least works for you.

Jeng

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The reason why I did not have JTAG access after PS configuration was hardware-related. The Microprocessor on the board coupled noise and spikes into the JTAG's TCK line, which caused state machine transitions into unexpected states.

But your problem sounds familiar to me as well. I observed it frequently with older quartus versions. Which version do you use?

Peter