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Altera_Forum
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13 years ago

Cyclone IV no JTAG access after PS configuration

Hi I use passive serial configuration for a EP4CE10F17C8 device (a DSP controls the nSTATUS, nCONFIG, DCLK and DATA0 ports of the FPGA) After configuration the FPGA releases CONF_DONE as it sho...
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Altera_Forum
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13 years ago

This is not an undocumented feature. There is something wrong with your hardware.

When you use the JTAG debugger, probe the JTAG pins. When you press the check IDCODE, the debugger will generate JTAG transitions on TCK and TMS to reset the JTAG TAP, which defaults to loading the IDCODE JTAG instruction. TCK and TMS will then be toggled to move the TAP into the Shift-DR state and the IDCODE should be output on TDO. See the attached scope trace.

If you don't see valid logic levels on these three signals, then you may have an issue. To test TDI, use the other tab of the debugger and move the TAP to the Shift-DR state, and enter a 32-bit value, eg., 0xAAAAAAAA. Then shift that into the TAP. The response will be the JTAG ID code, but TDI will be toggled.

Cheers,

Dave