Cyclone IV E JTAG issues - VCCA voltage level

Bummer, I must have made a mistake last night. All the rails are indeed correct. Which is good since I then did not miss a DRC error.

I measured each power pin on its via while triggering the scope on the nStatus pulse so make sure the rail is ok and that there is no voltage dip when the device tries to come out of reset. All pins are ok.

I attached 2 scope shots, one showing the recurring nStatus pulse and the second same pulse, but zoomed in a bit more.

I also attach the sch for the power and config page. (the pullups for the TDI and TMS and pulldown of TCK is on the top level at the connector). On the FPGA connection, where you see 1V2,# define to 1V and 1V8 is# define 2V5 after the rail adjustments I made. I am not planning on using any plls, this i did not bother with separating the pll rails from the int rails.

Let me know if you see something weird.

EDIT: If I pull nConfig low, the pulse on nStatus obviously goes away (device being in reset) and then reappears when nConfig released.

EDIT: did some more measurements and photo3 shows the nStatus pulse together with the DCLK signal.

Again, I appreciate the help.

Ivor