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Altera_Forum
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8 years ago

Cyclone IV configuration from 1.8V SoC

I want to configure a Cyclone IV part (EP4CE10F17C7) using passive serial mode from an onboard processor. The processor's I/O pins are all 1.8V logic level. I would think this would be fine if I se...
Altera_Forum's avatar
Altera_Forum
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7 years ago

Following up now that I have boards built ...

- Good news ... I've had no problems configuring the FPGA with 1.8V I/O pins!

- Summary of the setup:

  • Cyclone IV FPGA (EP4CE10F17C8)

  • 3 MSEL pins pulled to GND (Passive Serial configuration)

  • All banks powered by VCCIO=1.8V

  • Using 1.8V LVCMOS signals directly attached to a processor to configure the FPGA.

Despite this success, it does seem that there is some reason Altera doesn't want us to do this. In addition to the lack of 1.8V PS option in the handbook (which I previously described), we get a warning when building the project:

Warning (169201): I/O bank '1' VCCIO voltage is '1.8V', which is not supported for the 'Passive Serial' configuration scheme and the configuration device

Any idea how we find out why this is the case? Fortunately it does seem to be working ... I'm just concerned there is some condition where we may run into trouble.

Thanks again