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Altera_Forum
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10 years ago

cyclone IV asmi read problem

I have a problem in reading EPCS16 with asmi_parallel.

I can write configuration to EPCS with USB blaster, and FPGA configuring and working correctly. But when I try to read my hex data (address 0x70000 in EPCS or ANY other address, e.g. 0, 0x70200 etc) with asmi_parallel I'm getting FFs (all binary 1).

Signaltap shows that asmi module working correctly (see image), but nothing readed.

Device: cyclone IV E EP4CE6F17I7 FBGA-256, EPCS-16 SOIC-8

Quartus: 14.0 build 200 web edition

Code, OSC14 = 14.318 MHz


module bios_asmi(
  input wire OSC14,
  output wire BIOS_DONE,
  //interface to external SRAM where to write readed data
  output reg  RAM_A,
  output reg  RAM_D,
  output reg nWR);
wire  ASMI_DATA;
wire ASMI_BUSY, ASMI_DVALID;
//readed byte counter
reg  CNTR = 17'h0;
always @(posedge OSC14) CNTR <= ASMI_DVALID & ~BIOS_OK ? CNTR+17'h1 : CNTR;
wire PRELAST_BYTE = ~CNTR & (&CNTR); //FFFF
wire LAST_BYTE = CNTR;
//set RDEN on BUSY=0 and counter < done
reg RDEN = 1'b0;
always @(negedge OSC14) RDEN <= (PRELAST_BYTE | LAST_BYTE) ? 1'b0 : ~ASMI_BUSY | RDEN;
//set READ_CMD on RDEN front
reg RDEN_FRONT;
always @(negedge OSC14) RDEN_FRONT <= RDEN;
wire READ_CMD = RDEN & ~RDEN_FRONT;
//read done to other modules
reg BIOS_OK = 1'b0;
always @(posedge OSC14) BIOS_OK <= LAST_BYTE;
assign BIOS_DONE = BIOS_OK;
//latch data to word size register
always @(posedge OSC14) begin
  RAM_D <= ASMI_DVALID & CNTR ? ASMI_DATA : RAM_D;
  RAM_D <= ASMI_DVALID & ~CNTR ? ASMI_DATA : RAM_D;
end
//latch RAM address
always @(posedge OSC14) RAM_A <= ASMI_DVALID & CNTR ? {1'b0,4'hF,CNTR} : RAM_A;
//write RAM signal
always @(posedge OSC14) nWR <= ~(ASMI_DVALID & CNTR);
//asmi instance
parameter bios_read_addr = 24'h70000;
asmi_bios asmi(.clkin(OSC14), .read(READ_CMD), .rden(RDEN), .addr(bios_read_addr), .reset(1'b0), .dataout(ASMI_DATA), .busy(ASMI_BUSY), .data_valid(ASMI_DVALID));
endmodule

SignalTap:

http://www.alteraforum.com/forum/attachment.php?attachmentid=11530&stc=1

Schematics:

http://www.alteraforum.com/forum/attachment.php?attachmentid=11531&stc=1

All pins set as "regular io". I've tried other options (programming pin, compiler reserved etc) - no change.

Appreciate for help.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Problem solved.

    This module was intended to work immediately after FPGA configuration is done. But it just don't want to, idk why.

    So solution is: delay execution with a simple counter (64 pulses of OSC14 is enough, 16 is NOT enough).