Cyclone III Nios problem

You are getting memory errors due to the timing problems.

How far did you optimize your design to meet the timing requirememts? Maybe you still can activate some more optimization options and achieve a better timing. (e.g. Perform pyhsical synthesis for combinational logic, register duplication, register retiming, etc).

If that still doesnt help, maybe place the DDR in a design partition and compile it alone before you add the other modules.

How bad is your timing? How full is the FPGA?

Lokla