Honored Contributor
Honored Contributorfrom the altera knowledge base:
problem is a 10k pull-up resistor mandatory on the conf_done signal or can i use a 1k pull-up resistor? solution Yes, a 10k pull up resistor is mandatory on the CONF_DONE signal. A 1k pull-up resistor may cause CONF_DONE to rise too early, causing the target FPGA to reset and thus cause configuration failure. However, I had similar issues with the Conf_Done on the Cyclone 3 device in Active Serial mode where the Conf_Done did not rise fast enough. Just the opposite of the Altera note. The Cyclone 3 utilizes a faster configuration clock. I have to wonder if the timing of the status checks have increased proportionally as a result. Would be interesting to know. I'm looking to find more information regarding the timing on the Conf_Done, nStatus, etc upon configuration completion. Anyone have any good timing diagrams and specifications? Apparently, a status test routine samples the Conf_Done sometime after configuration completes. And, I currently don't understand what Altera is describing about Conf_Done rising too fast. In any case, I had one out of four boards that would successfully configure via Active Serial. All have 10K pull-ups on Conf_Done. If I add capacitance to the --working-- board (scope probe, tweezers, etc), the board will --not-- configure. As a result, it seems that the rise time was not fast enough. I replaced the 10K with 5K decreasing the rise time. Now the boards configure fine. I'm going to stick with the 5K until I can determine the root cause of the difference further. Please let me know if anyone is able to solve their problem by changing the pull-up as well. Regards, Jay Vicory
