Cyclone III EP3C120F780C7 @ 150MHz?

I unfortunately have not used Cyclone III at all. I am currently doing 1080p60 video with the 148.5MHz parallel clock but my design is a Stratix II GX. 150MHz is a walk in the park for that family.

Now in your case, I would not try to run your video processing clock at less than 148.5MHz. You might be able to go a little less than that but not much. I'm pretty sure you can hit the 148.5MHz target in the cyclone III.

As far as the frame buffer goes... Configure the frame buffer just as you have said. Match the width of the frame buffer's memory interface to match your DDR2 memory controller interface width. So for example, if you've got a 64-bit physical width memory (size of a DIMM), your normal local interface width to the DDR2 High-Performance controller would be 128 bits. However, the High-Performance controller also gives you the option of running the local interface at half the clock frequency and twice the data width (so 256 bits). The tradeoff is obviously the wider bus. Anyway, let's assume that you are going to use the full-rate interface rather than the half-rate. So you've got a 128-bit interface to the DDR2 controller.

You would configure the frame buffer as shown in the attached image.

Now there is an undocumented change you can make to the frame buffer that will allow you to run your video input and output on one clock and the memory interface on another.

Edit the file:

C:\altera\80\ip\frame_buffer\lib\vip_vfb_hwfast.hpp

Change line 13 from

# define VFB_MEM_MASTERS_USE_SEPARATE_CLOCK false

to

# define VFB_MEM_MASTERS_USE_SEPARATE_CLOCK true

Now when you create the Frame Buffer component in SOPC builder, your avalon streaming interface and avalon memory masters will be on different clocks. Connect the streaming interface to your video processing clock and the memory masters to the DDR2 controller interface clock.

This will allow you to run the memory interface at something less than 148.5 MHz.

What the frame buffer is going to do is write/read several 24-bit pixels to/from the memory in parallel.

Jake