Honored Contributor
Honored ContributorThanks for useful info. > all
@Jake It's me again who asked about DDR2 controller at another thread. My problem is, I have to output a 1080p60 video with pixel clock of 148.5MHz (according to the HDTV standard). To achieve this, the simplest way is to process video data at a clock of 148.5MHz (150MHz). From responses in this thread, I feel that 150MHz is a big challenge. I have to think about other solutions. Would you please tell me about yours: Have you ever output 1080p60 video using Cyclone III? How did you achieve that? Did you designs include any vendor's IP (such as Altera's VIP)? I will use Altera's Frame Buffer (comes with the VIP suite v8.0) as a 1080p60 video frame buffer. Its Avalon MM master's data width is 128 (interfaces with a DDR2 SDRAM controller) while its Avalon ST Source/Sink's data width is 24 (8-bit R,G,B parallel). How do I configure the Frame Buffer so that it can make use of 128-bit data buffering? If this were ok, I would process video data at clock of about 100MHz but still have pixels output at 148.5MHz? Sorry for asking many questions. I am relying heavily on all of you.... Thanks.
