Forum Discussion
Altera_Forum
Honored Contributor
12 years agoThat fully depends on what you implement inside your FPGA, how many PLLs, how fast your design will be clocked etc. If you do not have anything yet then this will be hard to predict.
That fully depends on what you implement inside your FPGA, how many PLLs, how fast your design will be clocked etc. If you do not have anything yet then this will be hard to predict.