Cyclone II PLL ESD Sensitivity

I already tried with a TCXO oscillator just next to the clock input. But it did not help.

I think you are right about the ground bounce, unfortunately it is quite difficult to impove in the current design.

I'm aware that temporary disturbances are allowed and a software workaround may be the solution.

I have based the FPGA internal reset signal on an external reset signal and the PLL "Locked" signal. If the PLL goes out of lock, then I reset all state machines. This will make the disturbance not just temporary as I will loose communication.

I believe it is best practice to reset the system if the PLL goes out of lock, but it actually seems that the state machines survives a discharge if I don't. Is it safe to run if the PLL goes out of lock?