Cyclone II PLL ESD Sensitivity

With Cyclone II, PLL supply interferences, including ground bounce affecting the PLL supply are the most likely cause for PLL loose of lock, according to my experiences. Interferences at the input clock are another possible reason.

Generally, the ESD may cause supply spikes, that are slow enough to cross the PLL supply filter. But without knowing your supply bypass topology and board layout, it's hard to decide. I expect, that you have a multilayer PCB with a continuous ground plane and effective bypass capacitors at all supply pins connected directly to this plane?

To suppress possible interferences at the input clock, you may solder a small crystal oscillator for test as near as possible to the FPGA, only connecting directly to FPGA pins.

As another point, ESD are allowed to cause temporary disturbances, that can be handled without user interaction in usual EMC rules. It's mainly a matter of software design to meet this requirement, at least as a last ressort to avoid a complete redesign.