Cyclone II : Configuration through Embedded JTAG

Vidya,

I don't know what is supposed to be sent out at TDO during device configuration. But if the data coming out at TDO is the same as this one sent to TDI but after ONE OR TWO clock cycles than this looks somewhat weird. I like to recommend that you write a small test program to test the reliability of the JTAG communication between uC and FPGA. Use the bypass instruction to select the bypass register in the FPGA as the TDO source. So TDO should drive the data sent into TDI with one clock delay. Send several million random bits and use you alredy implemented error counter to see if the communication is stable.

Concerning your questions: I cannot imagine that you can reach the limts with a micro controller executing some firmware. No way. You will hurt setup/hold requirements if you change TDI/TMS with the same instruction that causes the rising clock edge. But, according to you description, this is not the case.