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Honored Contributor
Honored ContributorCyclone II : Configuration through Embedded JTAG
Dear All, i am new to the FPGA world. I am using FPGA for signal processing. i have the *.rbf file. i want to load this file into FPGA SRAM.this the following step i m performing: ...
Altera_ForumHonored Contributor
Honored ContributorIn JTAG,
what ever is transmitted on FPGA_TDI port , same data is can be collected on FPGA_TDO port in the next clock cycle. Is it correct in case of transmitting the binary data from RBF file? when I read data from FPGA_TD0 pin i get the byte but it is shifted one bit. some time it is 2 bit shifted. i am incrementing counter if i get any mismatch and there is lots of byte that doesn't match with TDI port data. can you suggest possible reason for that? Is there any Limit for toggling I/O pin? what is the Max/Min clock frequency for FPGA configuration with JTAG interface?
