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Altera_Forum
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17 years ago

Cyclone II : Configuration through Embedded JTAG

Dear All, i am new to the FPGA world. I am using FPGA for signal processing. i have the *.rbf file. i want to load this file into FPGA SRAM.this the following step i m performing: ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

It looks quite correct what you are doing. Some comments concerning your questions:

1. How one should gerate clock?

You do it nearly perfect. Apply data, wait, apply rising clock edge, wait, apply falling clock edge.

3. Is there ant method for reading *.rbf file. any CRC check is there, if it is there how to verify it in code.

No, rbf is really raw. If you change 1 single bit you cannot figure that out but the FPGA will refuse to being configured

4. How to verify the all the bits are written properly?

No way.

It seems that you have donwloaded the jrunner source code and ported that to the embedded controller. I think there are some comments in that source code telling that for particular devices some bits at the very beginning must be disregarded. Maybe you should read the original source code in detail.