Cyclone II : Configuration through Embedded JTAG

I am using JRunner source code as refrence.

my goal: I want to configure FPGA with JTAG interface.

I have downloaded complete uncompressed RBF in external FLASH interfaced with microcontroller.

I am reading one byte from Flash and sending that byte on FPGA_TDI pin with LSB first.

problem:

1. How one should gerate clock? i am genrating it when i am riting byte to FPGA_TDI , toggling Microcontroller TCK pin Low to high transition.

writeport_data(unsigned char data)

{

if (data)

write 1 to FPGA_TDI pin

else

write 0

//genrate Riging Edge clock

TCK_Pin = Low

delay(20);

TCK_Pin = High

delay(20);

}

2. I am not able to figure out what is problem with my code.

3. Is there ant method for reading *.rbf file. any CRC check is there, if it is there how to verify it in code.

4. How to verify the all the bits are written properly?

present status of my code:

I am able run JTAG state machine correctly.

when ever i am sending the JTAG instruction on FPGA_TDI pin with rising clock edge, i am getting 10 bit sequence of "1010101010"(0x155) on FPGA_TDO pin. As mentioned in the Altera document(Cyclone II device Handbook volume-1 page no - 14-17).

when i send Read DEvice ID it gives the correct data on FPGA_TDO pin as mentioned earlier.

when i am sending the Programm Instruction it doesn't work.

how i m doing it is mention below in steps:

1.Got to RESET/RUN_IDLE state

2. Go to SHIFT_IR state

3. Send 10 bit Instruction Byte (0x002)

4. Go to SHIFT_DR state

5. send complete *.rbf file date with LSB bit first

6. sned 299 additional clock cycle (as mention in the Altera HAndbook page no-13-56 2nd paragraph) to initialize Cyclone II device.

7. then exit SHIFT_RD state.

after this switch to user mode by sending JTAG instruction 0x003.

when i read and write any register in FPGA it some time return 0x06, or 0xFF.

and LED is not working at all.

but when it is programmed through JTAG ByteBlaster it works fine.

system pin configuration details:

my system has one AT91R40008 microcontroller and one Cyclone II FPGA((EP2C20F256).

Four I/O pin of micro is connected to the JTAG port of FPGA.

nCONFIG pin is pulled up with 10K ohm registor.

CONFG_DONE pin is pulled up with 1K ohm registor.

I am keeping MSEL status as given in Altera Document.

MSEL1= to GND

MSEL0 to Vcc.