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Altera_Forum
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14 years ago

Cyclone 4 deserialization, banks, pll

Dear Gurus; I have 1 Cyclone IV GX EP4CGX150(DF27C7) This Cyclone IV is connected to 6 x Cyclone III (C40F484) All of these 6 Cyclone IIIs will send 4 bit LVDS serialized input data ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Yes there will be slow clock and there will be a fast clock

With the fast clock => deserialization will be done

With the slow clock => paralel data(N:0) will be latched for each slow cycle clock