Crossing clock domains, PLL and TimeQuest

Multicycles can do multiple things(look at TimeQuest User Guide on alterawiki.com), but most of the time users saying multicycle mean opening the window. So if I have a 10ns setup relationship(let's say both clocks are 10ns period), then a multicycle -setup 2(and multicycle -hold 1) will make the setup relationship 20ns while the hold relationship is 0ns. So now data can transfer anywhere between 0-20ns. This gives you twice as much margin to meet timing, but your data throughput is half, since you can only get data through every other cycle. The most common scenario is where a designer creates a clock enable from a toggle flip-flop, so the source and destination registers toggle every other cycle.

The key to this kind of multicycle is that you've designed for it, and now the default setup relationship is too restrictive. If it doesn't jump out at you right away that you've designed something that can be multicycled, then most likely it can't be. (Of course, there are exceptions to everything...)