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Altera_Forum
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13 years ago

Crossing clock domains, PLL and TimeQuest

Hi everybody, I worked on one project with one global clock f = 50 MHz. Then I had to modify this project. All logic inside is the same, but now, part of the project is working with clock f = 1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks a lot guys. It is more clear for me now.

I have just started looking into recommended literature.

But I have new question.

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To fix those setup failures, you need to look at the failing paths timing and logic.

Maybe you need to add some registers to the design to split the worse paths. Or maybe you need to set some multi-cycle exceptions to relax the timings requirements on those paths.

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How can I know which way I should go? From what does it depend?