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Altera_Forum
Honored Contributor
Honored ContributorCrossing clock domains, PLL and TimeQuest
Hi everybody, I worked on one project with one global clock f = 50 MHz. Then I had to modify this project. All logic inside is the same, but now, part of the project is working with clock f = 1...
Altera_ForumHonored Contributor
Honored ContributorThere's a great app note that helps address this: http://www.altera.com/literature/an/an545.pdf
We usually use 2 FF synchronizers, with a relaxed set_max_delay on the first FF. The guide above says you can false path it, but I'd rather give it some amount of time for setup.
