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Altera_Forum's avatar
Altera_Forum
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13 years ago

CRC Calculation - VHDL

Hello to all forum members!!! I'll be glad to get your's suggestions to solve my problem. I am interested to make the CRC Calculation as fast as possible (without using the MegaWizard function)...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

There is no point pipelining it - that would only be relevant if you wre trying to process a packet every clock (with a 53 clock delay before the crc was available).

Surely you can do the CRC as part of the tx dma? Then send the (inverted) CRC register at the end of the normal data buffer.