CRC Calculation - VHDL

--- Quote Start ---

How many bits do you receive in one clock cycle? I would compute the CRC with this number if bits in your case.

Lets say you receive 8 bits per clock cycle, this would results in a much smaller logic and meet your timing target easily.

--- Quote End ---

The number of bits dependent from what side do you want to look - transmitter or receiver.

* During transmission I get all the packet during one cycle time. One more cycle for CRC calculating and then I enable the transmission. After this I'm waiting the nest 10mSec to transmit another packet.

* During receiveing I get the bytes one by one.

If i'll separate the action on steps (step = one byte calculation). So I need something like 53 cycles to get the result.

how can I use the pipeline for it?

Or maybe onother one method the get the right results with minimum of actions.

TNX