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Altera_Forum's avatar
Altera_Forum
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13 years ago

CRC Calculation - VHDL

Hello to all forum members!!! I'll be glad to get your's suggestions to solve my problem. I am interested to make the CRC Calculation as fast as possible (without using the MegaWizard function)...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Which CRC are you computing?

Sounds a bit like CRC16.

You might be able to make use of the fact that you can XOR together two packets and still have a valid CRC (if you correctly allow for the initial value and final inversion).

So maybe you can xor together the CRC value for each bit.

While this is now 53*8 XORs, they can be done in parallel - so only 10 deep.

If large parts of the packet are fixed, they can be excluded from the dynamic crc.

OTOH why don't you defer the CRC calculation until teh data is serialised?

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I am computing CRC 16 CCITT

It is based on XORing the data with polynom. Every time I making shifting and XORing with the same polynom. After the execution of all packet I get the result build of 16 bit. I'm sure that you are familiar with it :)