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Altera_Forum
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15 years ago

CPLD I/O's during power up

Hello everybody, I am using a Max II EPM570T100A5 CPLD; in our design the CPLD controls 4 MOSFET drivers for a fullbridge, thus it is critical that these outputs on the CPLD remain at GND dur...
Altera_Forum's avatar
Altera_Forum
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15 years ago

For a safe design, you should put in minimum pull-up resistor value from the datasheet and maximum acceptable low-level of the interfaced peripheral.