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Do you mean that not all Cyclone V models come with the dedicated remote update hardware? The documentation doesn't mention this, as far as I could tell all of the CycV have the dedicated circuitry for this.
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I don't mean that. As far as I know the Altera remote update IP core is a softcore, not hardcore; i.e. It can exist in the FPGA using some logic cells or it may not exist at all if you do not want remote update feature. This means that existence of this IP core within your FPGA depends on its current configuration, which is in turn susceptible to SEUs.
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I'm aware what the pins are used for in the board, what's not clear to me is whether the pin will still be available for this other functions once I've checked the "Enable Error Detection CRC_ERROR pin" or if it'll be hardwired to the CRC function and no longer available to the application.
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One you enable the CRC option, that pin will be used for CRC feature. It cannot be used for any other purposes. It is available to you for error detection mechanisms & you can use it for error detection.
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