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Altera_Forum
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18 years ago

Counter simulation

I got a three bit counter module which reset to 3'b000 every sixth count of clock. when I simulated using quartus II 7.2, I found wrong numbers after count values of 1, 3 and 5. (That is simulation s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Surprizing result :D

This is, cause Quartus integrated synthesis is too clever in this case. It infers a state machine (with different coding), where no state machine is intended. See quartus handbook, vol 1, sect. iii.8 quartus ii integrated synthesis, quartus ii synthesis options, preserve registers

Knowing the problem, you can manage it easily: 

reg  cnt /* synthesis syn_preserve = 1 */;