Counter and time delay

The last version is basically correct. You should also review the HDL templates available in Quartus editor context menu.

I did'nt exactly understand your reset problem. The reset as shown is an asynchronous, level sensitive reset, don't be confused by the posedge keyword in this regard, it's required Verilog syntax but doesn't actually mean an edge. An asynchronous reset can be level sensitive only. The counter flip-flops can have only one clock input, that's the same situation as with any hardware counter IC.

Alternatively, you can have a synchronous reset that is operating in conjunction with clock input.