Counter and time delay

Another problem is in a counter I wrote. I works fine but how do I reset it with posedge reset?

I would like to write something like this but Quartus doesn't allow it:

always @ (posedge reset) begin

count <= 0:

end

always @ (posedge increaseCounter) begin

count <= count + 1;

end

The way I have it now is presented below:

always @ (posedge inc_counter or posedge reset) begin

if (reset) begin

count <= 16'b0000_0000_0000_0000;

end

else begin

count <= count + 1'b1;

end[/INDENT]

end

The problem is that reset keeps its value 1 and I don't want to reset counter then but only @ posedge reset. I remember I read somewhere how to check which posedge is the actual trigger but I couldn't find it again.