Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Correct Arria II GX ALTGX Reset Sequence?

I have designed a reset controller for my ALTGX-based PIPE interface per The Arria II GX handbook, Vol2 page 4-16. My goal is to be able to capture the PCIe compliance pattern sent out by a PC mother...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

We just had an Altera transceiver specialist in this last week and his recommendation with respect to resets was that rx_digital_reset should only be released after rx_freqlocked has remained high for 4us. In my opinion this is not very clear in the sequence diagrams but if you signaltap the pins you can see that rx_freqlocked toggles for a while once it goes active. The Altera guy said that it rx_freqlocked to be continuously asserted for 4us before releasing rx_digital_reset.

There's also a specific reset sequence for PCIe functional mode http://www.altera.com/literature/handbooks/wwhelp/wwhimpl/js/html/wwhelp.htm#href=stx4_siv52004.21.3.html

That was for stratix iv but maybe something similar for the ArriaII part?