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Altera_Forum
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15 years ago

Correct Arria II GX ALTGX Reset Sequence?

I have designed a reset controller for my ALTGX-based PIPE interface per The Arria II GX handbook, Vol2 page 4-16. My goal is to be able to capture the PCIe compliance pattern sent out by a PC mother...
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Altera_Forum
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15 years ago

I also tried the reset sequence described on page 4-13 in the Arria II GX handvook, Vol2. This keeps rx_digitalreset asserted until 4us after the CRU has locked to the data and rx_freqlocked asserts (automatic lock mode). The outcome is the same; pipestatus=4 (8b/10b decode error).

Updated files attached.

Any idea what to look for?