Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCordic core
hi im making a bit serial cordic in VHDL. i have written all the codes for the architecture but i cant figure out how to loop the architecture for n iterations. do i have to include a state machine??...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- 1) for the iteration looping, are you using a finite state machine to control? 2) for the shifting.. is it an sign extended shifting? or simply jus right shifting.. with zero replacing the MSB ? --- Quote End --- 1. you can use a register pipeline to propagate a 'valid' bit 2. if you have signed variables you use arithmetic shift, so you copy the MSB e.g. 1011 arithmetically shifted right becomes 1101
