Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Cordic core

hi im making a bit serial cordic in VHDL. i have written all the codes for the architecture but i cant figure out how to loop the architecture for n iterations. do i have to include a state machine??...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Did you read the code explanation in the pdf file?

--- Quote Start ---

unfortunately it doesnt sucessfully compile

--- Quote End ---

MaxplusII has limited HDL support. Why don't you change to Quartus?