Forum Discussion
Altera_Forum
Honored Contributor
15 years agoCordic core
hi im making a bit serial cordic in VHDL. i have written all the codes for the architecture but i cant figure out how to loop the architecture for n iterations. do i have to include a state machine??...
Altera_Forum
Honored Contributor
15 years agoOh Hi.. thx for the reply. Well, I saw that cookbook rar file too. But i tried to run the code given using maxplus2.. unfortunately it doesnt sucessfully compile. there are some part that i dont wuite und the coding as well.
i) reg last_xshift,last_yshift; always @(posedge clk) begin if (sclr) begin last_xshift <= 1'b0; last_yshift <= 1'b0; end else begin last_yshift <= yshift; last_xshift <= xshift; end end ii) // XYZ shift registers ////////////////////////////////// always @(posedge clk) begin if (sclr) begin x <= 0; y <= 0; z <= 0; end else begin x <= {(isel ? xi : xsum),x[WIDTH-1:1]}; y <= {(isel ? yi : ysum),y[WIDTH-1:1]}; z <= {(isel ? zi : zsum),z[WIDTH-1:1]}; end end assign xshift = sign_ext ? last_xshift : x[round_num]; assign yshift = sign_ext ? last_yshift : y[round_num]; assign xo = x[0]; assign yo = y[0]; assign zo = z[0]; can u pls explain what is the function of these coding if u understand it.. on top of that, I am also curious about 1) for the iteration looping, are you using a finite state machine to control? 2) for the shifting.. is it an sign extended shifting? or simply jus right shifting.. with zero replacing the MSB ? I really look forward for your reply and help. Thx in advance..