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Altera_Forum's avatar
Altera_Forum
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15 years ago

Cordic core

hi im making a bit serial cordic in VHDL. i have written all the codes for the architecture but i cant figure out how to loop the architecture for n iterations. do i have to include a state machine??...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

there is a Verilog CORDIC core in one of the Altera synthesis cookbooks. i ported it to VHDL for fun but i haven't run the simulation on the new code