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Altera_Forum's avatar
Altera_Forum
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15 years ago

Cordic core

hi im making a bit serial cordic in VHDL. i have written all the codes for the architecture but i cant figure out how to loop the architecture for n iterations. do i have to include a state machine??...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

I am working Cordic coding in Verilog using MaxplusII software. I am facing the same problem as you too.. which is the iteration looping of the coding.

I've tried module instantiation and also genvar looping.. but it doesnt works either. If you have got a solution, I be happy if you can share it with me.. Thx alot