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Altera_Forum
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15 years ago

Controlling Burst Mode in software

Hi. I have a verilog module that buffers a considerable amount of samples and when the buffer gets full id like to empty the buffer using a Nios processor for some computations. Using single IOR istr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I want the Nios processor to read my buffer in burst mode. In this case Nios processor is master and my buffer(custom component) is slave, right?